Error detection code (parity check code): parity check code consists of n-1 bit information unit and 1 bit check element. The N-1 bit information unit is the valid data in the information we send, and the 1-bit check unit is used for error detection and redundancy code.
Odd check: if the number of 1 in this series is even, add 1 in front of it, and the number of 1 becomes odd, otherwise add 0;
Even check: if the number of 1 in this series is odd, add 1 in front of it, and the number of 1 becomes even, otherwise add 0;
For example: (1) 1111 odd check is 11111 even check is 01111
(2) 1110 odd check is 01110 even check is 11110
The characteristic of parity check code is that it can only detect odd bit errors, and the error detection ability is 50%, which cannot be corrected.
Error detection code (CRC cyclic redundancy check code): it is a polynomial division method to detect errors. Each bit string is regarded as a polynomial, and modulo-2 operation is adopted.
The calculation process of the sending end is: the data frame to be sent + the check sequence of r bits, get the data frame to be sent, and then perform modulo-2 division with the generated polynomial to take the remainder, which is the FCS frame check sequence to be added.
The calculation process of the receiving end is: when the receiving end receives the frame, it performs modulo-2 division with the generated polynomial, and then checks the remainder. If the remainder is 0, it means that the transmission process is normal, and then accepts the data. If it is not 0, it means that the transmission process is abnormal, and then discards the data.
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